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LP5521
SNVS441F – JANUARY 2007 – REVISED FEBRUAY 2013
G CHANNEL PROGRAM COUNTER VALUE (G CHANNEL PC)
Address 0AH
Reset value 00H
Table 30. G Channel PC Register
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7
6
5
4
3
2
1
0
G_PC[3]
G_PC[2]
G_PC[1]
G_PC[0]
Name
G_PC
Bit
3:0
Access
R/W
Active
Description
G channel program counter value
PC registers are synchronized to 32 kHz clock. Delay between consecutive I 2 C writes to PC registers needs to
be longer than 153 μ s (typ.). PC register can be read or written only when EXEC mode is 'hold'.
B CHANNEL PROGRAM COUNTER VALUE (B CHANNEL PC)
Address 0BH
Reset value 00H
Table 31. B Channel PC Register
7
6
5
4
3
2
1
0
B_PC[3]
B_PC[2]
B_PC[1]
B_PC[0]
Name
B_PC
Bit
3:0
Access
R/W
Active
Description
B channel program counter value
PC registers are synchronized to 32 kHz clock. Delay between consecutive I 2 C writes to PC registers needs to
be longer than 153 μ s (typ.). PC register can be read or written only when EXEC mode is 'hold'.
STATUS/INTERRUPT REGISTER
Address 0CH
Reset value 00H
Table 32. STATUS/INTERRUPT Register
7
6
5
4
3
2
1
0
EXT_CLK
R_INT
G_INT
B_INT
USED
Name
Bit
Access
Active
Description
EXT_CLK
External clock state
USED
3
R
0 = Internal 32kHz clock used
1 = External 32kHz clock used
R_INT
G_INT
B_INT
2
1
0
R
R
R
High
High
High
Interrupt from R channel
Interrupt from G channel
Interrupt from B channel
Note: Register INT bits will be cleared when read operation to Status/Interrupt register occurs. INT output pin
(active low) will go high after read operation.
36
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